DocumentCode :
2982062
Title :
An architecture for compact associative memories with deca-ns nearest-match capability up to large distances
Author :
Mattausch, H.J. ; Gyohten, T. ; Soda, Y. ; Koide, T.
Author_Institution :
Hiroshima Univ., Japan
fYear :
2001
fDate :
7-7 Feb. 2001
Firstpage :
170
Lastpage :
171
Abstract :
Associative-memory architecture for Hamming-distance search, compact implementation, and short nearest-matches times up to large distances are proposed. The main ideas are fast analog word comparison and self-adaptive winner-line-up amplification. An implementation in a 0.6 /spl mu/m 2-poly 3-metal CMOS technology with 32 rows and 128 columns verifies the key concepts. Search time is <38 ns.
Keywords :
CMOS memory circuits; content-addressable storage; memory architecture; 0.6 micron; CMOS technology; Hamming-distance search; analog word comparison; associative memories; deca-ns nearest-match capability; search time; self-adaptive winner-line-up amplification; Circuit testing; Data compression; Feedback; Gray-scale; MOSFETs; Neural networks; Optical wavelength conversion; Pattern recognition; Time domain analysis; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
ISSN :
0193-6530
Print_ISBN :
0-7803-6608-5
Type :
conf
DOI :
10.1109/ISSCC.2001.912590
Filename :
912590
Link To Document :
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