Title :
A VHSIC demonstration radar signal processor
Author :
Fitzpatrick, John ; Vojir, William
Abstract :
An approach is being implemented that utilizes sophisticated computer-aided engineering (CAE) technology to facilitate meeting US Department of Defense advanced-technology-evaluation requirements for the Very High Speed Integrated Circuits (VHSIC) program. As a first step in this direction, a VHSIC Demonstration Radar Signal Processor (VDRSP) was designed, simulated, built, and tested. The VDRSP executes a standard moving-target-indication (MTI) function at a 5-MHz complex data rate. In order to minimize cost, schedule, and glue logic requirements, the VHSIC I IBM CMAC (Complex Multiply and Accumulate Chip) was selected for this project. The final system executes at a throughput of 450 million operations per second
Keywords :
VLSI; computerised signal processing; digital integrated circuits; radar equipment; 450 MOPS; 5 Mbit/s; 5-MHz complex data rate; CAE; Complex Multiply and Accumulate Chip; MTI; US Department of Defense; VDRSP; VHSIC I IBM CMAC; VHSIC demonstration radar signal processor; advanced-technology-evaluation requirements; computer-aided engineering; standard moving-target-indication; throughput; Circuit simulation; Circuit testing; Computational modeling; Computer aided engineering; Integrated circuit technology; Process design; Radar signal processing; Signal design; Signal processing; Very high speed integrated circuits;
Conference_Titel :
Aerospace and Electronics Conference, 1988. NAECON 1988., Proceedings of the IEEE 1988 National
Conference_Location :
Dayton, OH
DOI :
10.1109/NAECON.1988.194990
