Title :
A 900 MHz 2.25 MB cache with on-chip CPU now in Cu SOI
Author :
Hill, J.M. ; Lachman, J.
Author_Institution :
Hewlett-Packard Co., Fort Collins, CO, USA
Abstract :
The 500 MHz 1.5 MB cache with 50% increased bit count described is ported from a 0.25 /spl mu/m bulk technology to a 0.18 /spl mu/m SOI process with local interconnect. The SOI technology used presented significant design challenges to match the 80% frequency increase expected for the CPU.
Keywords :
cache storage; copper; field effect memory circuits; integrated circuit interconnections; silicon-on-insulator; 0.18 micron; 2.25 MByte; 900 MHz; Cu; SOI; Si; bit count; cache; design challenges; frequency increase; local interconnect; on-chip CPU; Capacitance; Decoding; Degradation; Delay; FETs; Frequency; Integrated circuit interconnections; Switches; Timing; Voltage;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912593
