A mixed-signal 0.18 /spl mu/m CMOS SOC for DVD systems with 432 MS/s PRML read channel and 16 Mb embedded DRAM

Author

Gotoh, S. ; Takahashi, T. ; Irie, K. ; Ohshima, K. ; Mimura, N. ; Aida, K. ; Maeda, T. ; Yamamoto, T. ; Sushihara, K. ; Okamoto, Y. ; Tai, Y. ; Nakajima, T. ; Usui, M. ; Ochi, T. ; Komichi, K. ; Matsuzawa, A.

Author_Institution

Matsushita Electr. Ind. Co. Ltd., Osaka, Japan

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

182

Lastpage

183

Abstract

A single-chip CMOS mixed-signal LSI for DVD systems contains 32 b RISC CPU, formatter, servo DSP, 16Mb DRAM, an ECC, ATA I/F, and digital read channel with 7b flash ADC. The chip in 0.18 /spl mu/m embedded DRAM process contains /sup 24/Rn transistors in a 144 mm/sup 2/ die. The data rate is 432 MSample/s with 1.2 W power consumption.

Keywords

CMOS integrated circuits; error correction codes; maximum likelihood detection; mixed analogue-digital integrated circuits; partial response channels; video discs; 0.18 micron; 1.2 W; 16 Mbit; 32 bit; CMOS; DVD systems; ECC; PRML read channel; SOC; data rate; digital read channel; embedded DRAM; formatter; power consumption; servo DSP; Circuits; Clocks; DVD; Error correction codes; Finite impulse response filter; Frequency synchronization; Large scale integration; Random access memory; Reduced instruction set computing; Signal sampling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912595

Filename

912595