DocumentCode
2982153
Title
A 700 Mb/s BiCMOS read channel integrated circuit
Author
Altekar, S. ; Chan, H. ; Jenn-Gang Chern ; Contreras, R. ; Leo Fang ; Hairong Gao ; Gee, R. ; Ha, P. ; Hsieh, K. ; Yenyu Hsieh ; Hsu, D. ; Xi Huang ; Kim, H. ; Kimura, H. ; Lai, P. ; Mohammed, I. ; Moser, L. ; Shih-Ming Shih ; Sugawara, M. ; Tamura, Y. ;
Author_Institution
LSI Logic Corp., San Jose, CA, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
184
Lastpage
185
Abstract
A read channel IC achieves >1.5 dB SNR improvement over a 32/34 rate EPRML read channel at 2.8 user bit density. The 0.18 /spl mu/m BiCMOS chip operates up to 700 Mb/s with 1.8 W read mode power using 3.3 V analog and 1.8 V digital power supplies. The die area is 9.64 mm/sup 2/.
Keywords
BiCMOS digital integrated circuits; maximum likelihood detection; partial response channels; 0.18 micron; 1.8 V; 1.8 W; 3.3 V; 700 Mbit/s; BiCMOS integrated circuit; EPRML read channel; BiCMOS integrated circuits; Bipolar transistors; Bit error rate; Block codes; Delay; Detectors; Finite impulse response filter; Ground penetrating radar; Magnetic heads; Magnetic separation;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912596
Filename
912596
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