A 300 MHz mixed-signal FDTS/DFE disk read channel in 0.6 /spl mu/m CMOS

Author

Wei, D.C. ; Sun, D.Q. ; Abidi, A.A.

Author_Institution

Integrated Circuits & Syst. Lab., California Univ., Los Angeles, CA, USA

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

186

Lastpage

187

Abstract

A 300 MHz mostly-analog DFE detector IC performs clock recovery and depth-of-two tree-search detection on equalized EPR4 waveforms. With MTR-coding, the detector is an analog DFE with digital error-correction logic to boost performance. At user density 3.0, performance exceeds that of an EPR4/VA channel. It consumes 530 mW from 3 V, and occupies 3.34 mm/sup 2/ active area.

Keywords

CMOS integrated circuits; decision feedback equalisers; mixed analogue-digital integrated circuits; partial response channels; synchronisation; tree searching; 0.6 micron; 3 V; 300 MHz; 530 mW; CMOS IC; EPR4 waveform; MTR coding; analog decision feedback equalizer detector; clock recovery; digital error correction logic; fixed delay tree search; mixed-signal FDTS/DFE disk read channel; Decision feedback equalizers; Delay lines; Detectors; FETs; Finite impulse response filter; Laboratories; Phase detection; Switches; Transconductors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912597

Filename

912597

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2982173