Scan-architecture-based evaluation technique of SET and SEU soft-error rates at each flip-flop in logic VLSI systems

A scan flip-flop (FF) is designed to observe both single event transient (SET) and single event upset (SEU) soft errors in logic VLSI systems. The SET and SEL´ soft errors mean the upset caused by latching an SET pulse that originates in combinational logic blocks and the upset caused by a direct ion hit to the FF, respectively. An irradiation test method using the scan FF is proposed to obtain SET and SEL soft-error rates at each FF distributed in logic VLSI systems. A test chip is designed using a 0.2-mum fully-depleted silicon-on-insnlator standard cell library. The basic concepts have been validated with Verilog timing simulations. The cell-level implementation costs of the proposed scan FF are estimated to be reasonable.