Low-Power 915MHz CMOS LNA Design Optimization Techniques for RFID

Author

Wu, Xiushan ; Sun, Ling ; Wang, Zhigong

Author_Institution

Southeast Univ., Nanjing

fYear

2007

fDate

18-21 April 2007

Firstpage

1

Lastpage

4

Abstract

According to the definition of noise figure, this paper presents a detailed analysis of the noise parameter of a low noise amplified (LNA) in a CMOS cascode topology with the source degeneration inductance and gate shunt capacitance. Based on the derived equations, the important application of this topology is discussed and a low power UHF CMOS LNA is optimized for RFID. The simulated results show a noise figure of 0.7dB, a power gain of 12.5dB, and an IIP3 of -4dBm while dissipating 2.1mA from a 1.8V supply. As a result, very low noise figures become possible already at very low power consumption levels.

Keywords

CMOS integrated circuits; UHF amplifiers; UHF integrated circuits; integrated circuit design; low noise amplifiers; low-power electronics; radiofrequency identification; CMOS cascode topology; RFID; UHF CMOS LNA; current 2.1 mA; design optimization techniques; frequency 915 MHz; gate shunt capacitance; low noise amplifier; low-power CMOS LNA; noise figure; source degeneration inductance; voltage 1.8 V; CMOS technology; Circuit noise; Circuit topology; Design optimization; Equations; Noise figure; Radiofrequency identification; Receivers; Signal to noise ratio; Sun;

fLanguage

English

Publisher

ieee

Conference_Titel

Microwave and Millimeter Wave Technology, 2007. ICMMT '07. International Conference on

Conference_Location

Builin

Print_ISBN

1-4244-1049-5

Electronic_ISBN

1-4244-1049-5

Type

conf

DOI

10.1109/ICMMT.2007.381397

Filename

4266156