Comparative Study of Si, Ge and InAs based Steep SubThreshold Slope Tunnel Transistors for 0.25V Supply Voltage Logic Applications

This paper examines the potential of double gate (DG) inter-band tunnel FETs (TFET) in 3 different material systems, Si, Ge and InAs, for logic circuit applications down to 0.25 V supply voltage (V_CC). Based on two-dimensional numerical drift-diffusion simulations, we show that 30 nm gate length (LG) InAs (indium arsenide) based TFETs can achieve I_on/I_off of >4x10⁴ with <1 ps intrinsic delay at 0.25 V V_CC. The key features of the InAs TFETs are: (a) asymmetric source drain design to suppress the ambipolar leakage (b) use of a lower dielectric constant gate oxide (non high-K) and (c) high source side injection velocity at moderate electric fields. Thus, narrow bandgap semiconductor based DG TFETs provide a promising device option for ultra-low standby and dynamic power high-speed logic circuits operating under quarter volt supply voltages.