Title :
An 8-Gb/s Half-Rate Clock and Data Recovery Circuit
Author :
Khalek, Faizal ; Sulaiman, Mohd-Shahiman ; Yusoff, Zubaida
Author_Institution :
Multimedia Univ., Cyberjaya
Abstract :
This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18 u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35 ps to 110 ps. While the data output jitter p-p is 4.6 ps and the clock jitter p-p is 6.6 ps. The power consumption is 55 mW from a 1.8 V voltage supply.
Keywords :
clocks; jitter; logic design; phase detectors; synchronisation; bit rate 8 Gbit/s; data recovery circuit design; half-rate clock; jitter; linear phase detector; power 55 mW; size 0.18 mum; voltage 1.8 V; Charge pumps; Circuits; Clocks; Detectors; Filters; Frequency; Jitter; Phase detection; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0637-1
Electronic_ISBN :
978-1-4244-0637-1
DOI :
10.1109/EDSSC.2007.4450180
