An 8-Gb/s Half-Rate Clock and Data Recovery Circuit

This paper presents circuit design and simulation result of the 8-Gb/s half-rate clock and data recovery circuit (CDR) by 0.18 u process technology. The linear phase detector was used for the CDR and able to give linear relation of the phase error between 35 ps to 110 ps. While the data output jitter p-p is 4.6 ps and the clock jitter p-p is 6.6 ps. The power consumption is 55 mW from a 1.8 V voltage supply.