DocumentCode :
2982432
Title :
A 0.6-2.5 GBaud CMOS tracked 3/spl times/ oversampling transceiver with dead-zone phase detection for robust clock/data recovery
Author :
Yongsam Moon ; Deog-Kyoon Jeong ; Gijung Ahn
Author_Institution :
Seoul Nat. Univ., South Korea
fYear :
2001
fDate :
7-7 Feb. 2001
Firstpage :
212
Lastpage :
213
Abstract :
Tracked 3/spl times/ oversampling with dead-zone phase detection is used in a receiver for robust clock/data recovery in the presence of excessive jitter and ISI. The transceiver, in 0.25 /spl mu/m CMOS, operates at 2.5 GBaud over 10 m 150 /spl Omega/ STP cable and at 1.25 GBaud over 25 m with <10/sup -13/ BER.
Keywords :
CMOS integrated circuits; intersymbol interference; jitter; phase detectors; signal sampling; synchronisation; transceivers; 0.25 micron; 10 to 25 m; BER; CMOS tracked oversampling transceiver; ISI; STP cable; clock/data recovery; dead-zone phase detection; jitter; Cable TV; Clocks; Delay; Detectors; Frequency; Phase detection; Phase locked loops; Robustness; Transceivers; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
ISSN :
0193-6530
Print_ISBN :
0-7803-6608-5
Type :
conf
DOI :
10.1109/ISSCC.2001.912608
Filename :
912608
Link To Document :
بازگشت