DocumentCode
2982445
Title
Investigation of Electrostatic Charges Trapping during 12-Inch Deep Submicron VLSI Proces
Author
Chen, Po-Ying ; Chen, S.L. ; Tsai, M.H. ; Jing, M.H. ; Lin, T.-C.
Author_Institution
I-Shou Univ., Kaohsiung
fYear
2007
fDate
20-22 Dec. 2007
Firstpage
549
Lastpage
552
Abstract
As semiconductor substrate wafer size and the manufacturing process steps are continuous to increase, several reliability concerns will become more important. This investigation considers in detail a defect called "silicon substrate damaged defects" and also introduces these defects\´ forming mechanisms and their root causes. The data of surface charge analyzer (SCA) measurement reveal that the electrostatic charges distribute on the wafer surface at the edge location thus attracting the carbon content of organic vapor during manufacturing process and resulting in defects occurring.
Keywords
VLSI; carbon; silicon; surface charging; Si; carbon content; deep submicron VLSI process; defects´ forming mechanisms; electrostatic charge trapping; organic vapor; silicon substrate damaged defects; size 12 inch; surface charge analyzer measurement; wafer surface; Electrostatics; Oxidation; Pollution measurement; Rough surfaces; Silicon; Substrates; Surface contamination; Surface morphology; Surface roughness; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location
Tainan
Print_ISBN
978-1-4244-0637-1
Electronic_ISBN
978-1-4244-0637-1
Type
conf
DOI
10.1109/EDSSC.2007.4450183
Filename
4450183
Link To Document