Title :
A 2.75 Gb/s CMOS clock recovery circuit with broad capture range
Author :
Anand, S.B. ; Razavi, B.
Author_Institution :
California Univ., Los Angeles, CA, USA
Abstract :
A dual-loop PLL clock-recovery circuit uses a digital search algorithm to increase capture range with no external reference. A 0.25 /spl mu/m CMOS circuit has 350 MHz capture range around 2.7 GHz, and 5.1 ps rms jitter consuming 50 mW from 2.7 V.
Keywords :
CMOS digital integrated circuits; digital phase locked loops; synchronisation; timing jitter; 0.25 micron; 2.7 GHz; 2.7 V; 2.75 Gbit/s; 50 mW; CMOS clock recovery circuit; capture range; digital search algorithm; dual-loop PLL; jitter; CMOS technology; Capacitors; Clocks; Counting circuits; Frequency locked loops; Optical noise; Phase locked loops; Tuning; Voltage control; Voltage-controlled oscillators;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912609
