A 28.5 GB/s CMOS non-blocking router for terabit/s connectivity between multiple processors and peripheral I/O nodes

Author

Nair, R. ; Borkar, N.Y. ; Browning, C.S. ; Dermer, G.E. ; Eriaguntla, V. ; Govindarajulu, V. ; Pangal, A. ; Prijic, J.D. ; Rankin, L. ; Seligman, E. ; Vangal, S. ; Wilson, H.A.

Author_Institution

Microprocessor Res. Labs., Intel Corp., Hillsboro, OR, USA

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

224

Lastpage

225

Abstract

A 28.5 GB/s data router enables a terabits/s bandwidth network. The 6.6M transistor 0.18 /spl mu/m 1.3 V 15 W CMOS LSI has three clocking domains that synchronize data through four 1.06 GB/s links, a B-port crossbar, and five point-to-point links of 4.75 GB/s data throughput each. Test data rates are up to 6.4 Gb/s per wire.

Keywords

CMOS digital integrated circuits; clocks; large scale integration; network routing; synchronisation; 0.18 micron; 1.3 V; 15 W; 28.5 GB/s; 6.4 Gbit/s; B-port crossbar switch; CMOS LSI; Stellar architecture; bandwidth; clock; high-speed digital communication; multiple processors; network connectivity; nonblocking data router; peripheral I/O nodes; point-to-point link; synchronization; throughput; CMOS process; Clocks; Driver circuits; Heat sinks; Impedance; Integrated circuit interconnections; Packaging; Phase locked loops; Round robin; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912614

Filename

912614