DocumentCode
2982585
Title
40 Gb/s ASIC switch design using low-jitter clock recovery
Author
Pathak, V. ; Ghing-Hao Shaw ; Vance, B. ; Devalapalli, S. ; Smith, P. ; Bonelli, A. ; Ribo, J. ; Bonte, O. ; Bauduin, F. ; Roderer, B. ; Verghese, M. ; Grant, L. ; Mah, H. ; Kean, C. ; Begin, P.
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
226
Lastpage
227
Abstract
A 32/spl times/32 switch ASIC has 40 Gb/s aggregate throughput. The switch fabric is realized in three stages using full-custom clock recovery and transmit ports at 1.25 Gb/s. 18 ASICs fabricated in 0.18 /spl mu/m CMOS technology and packaged in 352-pin flip-chip BGA dissipate 160 W.
Keywords
CMOS digital integrated circuits; application specific integrated circuits; ball grid arrays; flip-chip devices; integrated circuit packaging; semiconductor switches; synchronisation; timing jitter; 0.18 micron; 160 W; 40 Gbit/s; ASIC switch; CMOS chip; clock recovery circuit; flip-chip BGA package; jitter; throughput; Application specific integrated circuits; CMOS logic circuits; CMOS technology; Clocks; Data mining; Fabrics; Logic arrays; Optical design; Payloads; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912615
Filename
912615
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