• DocumentCode
    2982588
  • Title

    Optimization of n-channel tunnel FET for the sub-22nm gate length regime

  • Author

    Nikam, Vishwanath ; Bhuwalka, Krishna K. ; Kottantharayil, Anil

  • Author_Institution
    Dept. of Electr. Eng., IIT Bombay, Mumbai
  • fYear
    2008
  • fDate
    23-25 June 2008
  • Firstpage
    77
  • Lastpage
    78
  • Abstract
    In this work we explore for the first time, the design space for n-channel T-FETs with gate lengths below 22 nm using extensive device simulations. We show that the heterojunction tunnel-FET can satisfy ITRS requirements for HP and LSTP can be achieved using a SiGe-source device by an optimum choice of gate dielectric thickness and Ge fraction in Si1-gammaGegamma.
  • Keywords
    Ge-Si alloys; high electron mobility transistors; nanoelectronics; semiconductor materials; tunnel transistors; FET gate length regime; Ge-Si; HP; ITRS requirements; LSTP; extensive device simulation; gate dielectric thickness; n-channel tunnel FET optimization; size 22 nm; Degradation; FETs; Germanium silicon alloys; Heterojunctions; Leakage current; Medical simulation; PIN photodiodes; Photonic band gap; Silicon germanium; Tunneling;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Device Research Conference, 2008
  • Conference_Location
    Santa Barbara, CA
  • ISSN
    1548-3770
  • Print_ISBN
    978-1-4244-1942-5
  • Electronic_ISBN
    1548-3770
  • Type

    conf

  • DOI
    10.1109/DRC.2008.4800742
  • Filename
    4800742
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2982588