FPGA — Based fast SSCH detector for 3G WCDMA systems using cyclic Hierarchical codes

In 3G asynchronous WCDMA, the downlink receivers spent much time on acquisition and synchronization due to large computation time of the correlation and the detection of large codes (512) used. The work here deals with a reconfigurable FPGA design using VHDL hardware description language to provide realization of frame synchronization and code group identification to be complied with the 3GPP standard. The implementation is based on cyclic Hierarchical codes which show better cross correlation properties than that of CFRS (Comma Free Reed Solomon) codes. The proposed structure complexity is relatively low compared with that for CFRS: we need just one correlator instead of 16 and (32*16) ROM instead of (64*60) is required. A low complexity approximation is used to calculate the true magnitude of signals. Also different clock frequencies for correlation calculation are used. As a result, one slot is sufficient to obtain frame synchronization.