Title :
A 1.1 GHz first 64 b generation 2900 microprocessor
Author :
Curran, B. ; Camporese, P. ; Carey, S. ; Yuen Chan ; Yiu-Hing Chan ; Clemen, R. ; Crea, R. ; Hoffman, D. ; Koprowski, T. ; Mayo, M. ; McPherson, T. ; Northrop, G. ; Sigal, L. ; Smith, H. ; Tanzi, F. ; Williams, P.
Author_Institution :
IBM Server Dev., Poughkeepsie, NY, USA
Abstract :
The first 64 b S/390 microprocessor implemented in a 0.18 /spl mu/m, 7-level copper interconnect bulk CMOS process, runs operating system and applications at 1.1 GHz. The frequency is achieved with interconnect width and repeater optimization, selective use of low-Vt devices, tapered library gates, and improved synthesis and circuit tuning algorithms.
Keywords :
CMOS digital integrated circuits; high-speed integrated circuits; microprocessor chips; 0.18 micron; 1.1 GHz; 2900 microprocessor; 35 W; 64 bit; 7-level Cu interconnect; CMOS process; Cu; S/390 microprocessor architecture; circuit tuning algorithms; interconnect width optimization; low-Vt devices; repeater optimization; tapered library gates; CMOS process; Circuit optimization; Circuit synthesis; Copper; Frequency synthesizers; Integrated circuit interconnections; Libraries; Microprocessors; Operating systems; Repeaters;
Conference_Titel :
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location :
San Francisco, CA, USA
Print_ISBN :
0-7803-6608-5
DOI :
10.1109/ISSCC.2001.912620
