Title :
Self-Aligned n-channel MOSFET on InP and In0.53Ga0.47As Using Physical Vapor Deposition HfO2 and Silicon Interface Passivation Layer
Author :
Ok, Injo ; Kim, H. ; Zhang, M. ; Zhu, F. ; Zhao, H. ; Park, S. ; Yum, J. ; Garcia, Domingo ; Majhi, Prashant ; Goel, N. ; Tsai, W. ; Gaspe, C.K. ; Santos, M.B. ; Lee, Jack C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of Texas, Austin, TX
Abstract :
Research on high-k (HfO2) materials has been expanded significantly. However, MOSFETs with high-k gate dielectrics on silicon still have several problems with relatively low mobility of high-k devices in thin EOT regime compared to the universal curve. In this work, as an alternative of silicon substrate, InP and In0.53Ga0.47As has been studied. W e present the material and electrical characteristics of TaN/HfO2/InP self-aligned n-MOSFET with PVD Si interface Passivation layer (IPL) under various post deposition anneal (PDA) conditions. We also demonstrated N-channel high-k InP and In0.53Ga0.47As MOSFETs with good transistor behavior.
Keywords :
III-V semiconductors; MOSFET; electric properties; passivation; substrates; vapour deposition; In0.53Ga0.47As; InP; PVD Si interface passivation layer; electrical characteristics; high-k devices; high-k gate dielectrics; high-k materials; low mobility; material characteristics; physical vapor deposition; post deposition anneal condition; self-aligned n-MOSFET; self-aligned n-channel MOSFET; silicon interface passivation layer; silicon substrate; thin EOT regime; universal curve; Atherosclerosis; Dielectric substrates; Electric variables; Hafnium oxide; High K dielectric materials; High-K gate dielectrics; Indium phosphide; MOSFET circuits; Passivation; Silicon;
Conference_Titel :
Device Research Conference, 2008
Conference_Location :
Santa Barbara, CA
Print_ISBN :
978-1-4244-1942-5
Electronic_ISBN :
1548-3770
DOI :
10.1109/DRC.2008.4800749
