A high performance SI memory cell

In this paper we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching which leads to a high accuracy cell with measured errors of 200 ppm over a large range of input currents. The measured conversion rate is 700 ns. which is significantly high compared to other results presented in the literature. Still higher speeds can certainly be obtained by using technology processes which allow smaller transistor dimensions