Title :
A high performance SI memory cell
Author :
Leenaerts, D.M.W. ; Leeuwenburgh, A.J. ; Persoon, G.G.
Author_Institution :
Dept. of Electr. Eng., Eindhoven Univ. of Technol., Netherlands
Abstract :
In this paper we present a new type of switched current memory cell with a three phase clock cycle. The design technique is based on differential error matching which leads to a high accuracy cell with measured errors of 200 ppm over a large range of input currents. The measured conversion rate is 700 ns. which is significantly high compared to other results presented in the literature. Still higher speeds can certainly be obtained by using technology processes which allow smaller transistor dimensions
Keywords :
MOS memory circuits; analogue processing circuits; analogue storage; cellular arrays; switched current circuits; 700 ns; conversion rate; design technique; differential error matching; input currents; switched current memory cell; technology processes; three phase clock cycle; transistor dimensions; Capacitance; Circuits; Clocks; Current measurement; MOS devices; MOSFETs; Signal processing; Silicon compounds; Switches; Threshold voltage;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519185
