Title :
Design and implementation of a 100 MHz reorder buffer
Author :
Wallace, Steven ; Dagli, Nirav ; Bagherzadeh, Nader
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., Irvine, CA, USA
Abstract :
A reorder buffer is an important part of a superscalar microprocessor architecture. It allows out-of-order issue and completion of instructions, which contribute to overall performance enhancement. A custom layout of a 32-entry reorder buffer was implemented using a 1.0 μm (drawn) triple-metal CMOS technology. It measures 2 mm by 2.85 mm. The design was verified using several benchmark programs
Keywords :
CMOS digital integrated circuits; buffer storage; computer architecture; digital signal processing chips; integrated circuit design; 1.0 micron; 100 MHz; DSP chips; benchmark programs; custom layout; instruction completion; out-of-order issue; performance enhancement; reorder buffer; superscalar microprocessor architecture; triple-metal CMOS technology; CADCAM; CMOS technology; Computer aided manufacturing; Computer architecture; Decoding; High performance computing; Microprocessors; Out of order; Read-write memory; Registers;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519186
