Title :
Measurement of the main limitations of current memory cells
Author :
Moeneclaey, Nicolas ; Kaiser, Andreas
Author_Institution :
Dept. ISEN, CNRS, Lille, France
Abstract :
A test circuit topology to measure the main limitations of current memory cells requiring no dedicated instrumentation such as probe testing is proposed. The principles for measuring the settling time, the dynamic and static output conductance and the charge injection ratio are given. We also present a practical test circuit realized in a 1.2 μm CMOS technology, implementing several cascoded memory cells used in an 11 bit sigma-delta modulator
Keywords :
CMOS memory circuits; integrated circuit testing; network topology; 1.2 micron; 11 bit; CMOS technology; cascoded memory cells; charge injection ratio; current memory cells; dynamic output conductance; measurement technique; settling time; sigma-delta modulator; static output conductance; test circuit topology; CMOS memory circuits; CMOS technology; Charge measurement; Circuit testing; Circuit topology; Current measurement; Delta-sigma modulation; Instruments; Probes; Time measurement;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519189
