FPGA based implementation of FAST and BRIEF algorithm for object recognition

Author

Hoon Heo ; Jung-yong Lee ; Kwang-yeob Lee ; Chan-ho Lee

Author_Institution

Dept. of Comput. Eng., Seokyeong Univ., Seoul, South Korea

fYear

2013

fDate

22-25 Oct. 2013

Firstpage

1

Lastpage

4

Abstract

In this paper, we implemented the conventional FAST and BRIEF algorithm as hardware on Zynq-7000 SoC Platform. Previous feature-based hardware accelerator is mostly implemented using the SIFT or SURF algorithm, but it requires excessive internal memory and hardware cost. The proposed FAST & BRIEF accelerator reduces approximately 57% of internal memory usage and 70% of hardware cost compared to the conventional SIFT or SURF accelerator, and it processes 0.17 pixel per clock.

Keywords

feature extraction; field programmable gate arrays; object recognition; system-on-chip; BRIEF algorithm; FAST algorithm; FPGA; SIFT accelerator; SURF accelerator; Zynq-7000 SoC platform; feature-based hardware accelerator; field programmable gate array; memory usage; object recognition; scale-invariant feature transform; speeded-up robust features; system-on-chip; Computer vision; Feature extraction; Hardware; Object recognition; Random access memory; Registers; System-on-chip; BRIEF; FAST; Hamming Distance;

fLanguage

English

Publisher

ieee

Conference_Titel

TENCON 2013 - 2013 IEEE Region 10 Conference (31194)

Conference_Location

Xi´an

ISSN

2159-3442

Print_ISBN

978-1-4799-2825-5

Type

conf

DOI

10.1109/TENCON.2013.6718842

Filename

6718842