• DocumentCode
    2983051
  • Title

    A 1 V 12 mW 2 GHz receiver with 49 dB image rejection in CMOS/SIMOX

  • Author

    Ugajin, M. ; Kodate, J. ; Tsukahara, T.

  • Author_Institution
    NTT Telecommun. Energy Labs., Kanagawa, Japan
  • fYear
    2001
  • fDate
    7-7 Feb. 2001
  • Firstpage
    288
  • Lastpage
    289
  • Abstract
    One of the most effective ways of reducing power is to minimize the supply voltage, and the LC-tuned folded mixer is one way to achieve this. For cost reduction, a fully-integrated image-rejecting receiver, i.e. one for which off-chip filters are not required, is a desirable target. A double-quadrature downconverter is usually used to provide sufficient image rejection because the signal is transformed so that gain mismatches and phase errors in the converter inputs are reduced to second-order at the converter outputs. However, the double-quadrature architecture consumes much power because six mixers are used. In spite of its single-quadrature architecture, this 2 GHz receiver suppresses phase errors in LO signals and achieves 49 dB image rejection without trimming.
  • Keywords
    CMOS integrated circuits; SIMOX; UHF integrated circuits; low-power electronics; radio receivers; 1 V; 12 mW; 2 GHz; CMOS/SIMOX receiver; LC-tuned folded mixer; image rejection; low-power operation; single-quadrature architecture; Costs; Filters; Image converters; Impedance matching; Inductors; Noise figure; Power supplies; RF signals; Resonant frequency; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • ISSN
    0193-6530
  • Print_ISBN
    0-7803-6608-5
  • Type

    conf

  • DOI
    10.1109/ISSCC.2001.912641
  • Filename
    912641