• DocumentCode
    298324
  • Title

    Synthesis of fully testable combinational circuits

  • Author

    Evans, Allison H. ; Macii, Enrico ; Poncino, Massimo

  • Author_Institution
    Dept. of Comput. Sci., California Univ., San Diego, La Jolla, CA, USA
  • Volume
    1
  • fYear
    1994
  • fDate
    3-5 Aug 1994
  • Firstpage
    230
  • Abstract
    In this paper we present a procedure to insure the testability for single and multiple stuck-at faults of redundant, two level circuits, which are hazard free for single and and multiple input changes. The algorithm improves the performance of a previously published procedure, and can be implemented with existing integrated circuits (PLAs) without any modification
  • Keywords
    combinational circuits; design for testability; logic design; logic testing; redundancy; fully testable combinational circuits; redundant two level circuits; stuck-at faults; testability; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Computer science; Costs; Hazards; Input variables; Logic functions; Logic testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
  • Conference_Location
    Lafayette, LA
  • Print_ISBN
    0-7803-2428-5
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1994.519228
  • Filename
    519228
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=298324