DocumentCode
2983312
Title
A 1.8 GHz Instruction Window Buffer
Author
Leenstra, J. ; Pille, J. ; Mueler, A. ; Sauer, W. ; Sautter, R. ; Wendel, D.
Author_Institution
IBM Entwicklung GmbH, Boeblingen, Germany
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
314
Lastpage
315
Abstract
An Instruction Window Buffer (IWB) addresses the challenges in microprocessor designs beyond a GHz. The IWB implements the processor parts for renaming, reservation station and reorder buffer as a unified buffer. Measured results on an experimental chip demonstrate operation of the IWB macros at 1.8 GHz, with the chip at the fast end of the process distribution. The technology is 0.18 /spl mu/m CMOS8S bulk technology with 7 levels of copper interconnect and a 1.5 V supply. The IWB is implemented using static and delayed reset dynamic circuit macros.
Keywords
CMOS digital integrated circuits; buffer circuits; microprocessor chips; 0.18 micron; 1.5 V; 1.8 GHz; CMOS8S bulk technology; IWB macro; Instruction Window Buffer; microprocessor; CMOS technology; Copper; Delay; Filters; Integrated circuit interconnections; Logic arrays; Microprocessors; Out of order; Radio frequency; Semiconductor device measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912653
Filename
912653
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