A low power SOI adder using reduced-swing charge recycling circuits

Power reduction is a critical requirement in modern VLSI design due to increasing operating frequencies and circuit densities, and the emergence of portable applications. Decreasing the supply voltage, V/sub DD/, is the easiest way to reduce power consumption in CMOS circuits because switching power is proportional to V/sub DD//sup 2/ for rail-to-rail logic swing. However, reducing V/sub DD/ degrades circuit speed due to the super-linear reduction of transistor current. Lowering transistor threshold voltage, V/sub th/, helps to recover this speed degradation; however sub-threshold leakage current increases exponentially with decreasing V/sub th/, resulting in battery-draining quiescent power consumption with V/sub th/ less than about 300 mV. Circuit techniques are needed to achieve lower power consumption without speed degradation. The low-power CMOS SOI circuit configuration reported here, low-swing charge recycling (LSCR), uses differential pass-transistor logic, a low voltage swing, and charge recycling to save power.