Design and migration challenges for an Alpha microprocessor in a 0.18 /spl mu/m copper process

Author

Hokinson, R. ; Benschneider, B. ; Arneborn, M. ; Clay, D. ; Clouser, J. ; Dumford, S. ; Kalathur, V. ; Kalidindi, V. ; Kovvali, S. ; Krause, J. ; Maresh, S. ; Munger, B. ; O´Neill, N. ; Pragaspathy, I. ; Qin, W. ; Sasamori, R. ; Sayadi, S. ; Singh, T. ; T

Author_Institution

Compaq Comput. Corp., Shrewsbury, MA, USA

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

320

Lastpage

321

Abstract

An Alpha microprocessor design is implemented in a 0.18 /spl mu/m CMOS process, utilizing 7 layers of copper interconnect. Process features include nominal and low Vt transistor options, low-K FSG dielectric and a refractory metal local interconnect layer. The design is leveraged from a 0.35 /spl mu/m aluminum design. It contains 15.5M transistors on a 10/spl times/12 mm/sup 2/ die and is packaged in a flip chip ceramic land grid array. The microprocessor runs with a 1.65 V nominal supply and consumes 65 W. This microprocessor operates at >1.3 GHz.

Keywords

CMOS digital integrated circuits; copper; integrated circuit design; integrated circuit interconnections; microprocessor chips; 0.18 micron; 1.3 GHz; 1.65 V; 65 W; Alpha microprocessor design; CMOS process; Cu; copper interconnect; flip chip ceramic land grid array package; low-K FSG dielectric; refractory metal interconnect; Aluminum; Capacitance; Computer aided manufacturing; Copper; Energy consumption; Foundries; Integrated circuit interconnections; LAN interconnection; Microprocessors; Packaging;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912656

Filename

912656