Title :
Grouping of processors, memories and buses in the tightly coupled multiprocessor system
Author :
Chaudhry, G.M. ; Khan, A.N.
Author_Institution :
Dept. of Electr. & Comput. Sci., Missouri Univ., Kansas City, MO, USA
Abstract :
A new multiprocessor model using multiple bus as the interconnection network is presented. In this model N processors, B buses and H memory modules are connected in groups. The collapse of one or more of those memory modules, processors, and buses can lead to a loss in the performance of the whole system, if not collapsed completely. A scheme called the graceful degradable scheme for the reconfiguration of processors is presented. Thus, the system becomes a multiple group multiple bus system. The bandwidth of every multiple bus system is calculated and summed together to calculate the bandwidth of the whole system
Keywords :
distributed memory systems; fault tolerant computing; multiprocessor interconnection networks; bandwidth calculation; graceful degradable scheme; interconnection network; memory modules; multiple bus; multiple group multiple bus system; multiprocessor model; tightly coupled multiprocessor system; Bandwidth; Cities and towns; Costs; Degradation; Fault tolerant systems; Interleaved codes; Laboratories; Multiprocessing systems; Multiprocessor interconnection networks; Telecommunication network reliability;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519243
