Title :
Modeling of On-Wafer Interconnect System for CMOS RFICs
Author :
Shi, X. ; Yeo, K.S. ; Do, M.A. ; Boon, C.C.
Author_Institution :
Nanyang Technol. Univ., Singapore
Abstract :
In this paper, method of characterizing and modeling interconnects on metal layers beneath the top metal layer is proposed. Model development methodology for the complete on-wafer interconnect system, including interconnects on the top metal layer, interconnects on other metal layers and vias connecting different metal layers, is also presented.
Keywords :
CMOS integrated circuits; integrated circuit interconnections; radiofrequency integrated circuits; CMOS RFIC; metal layer; model development; on-wafer interconnect system; radio frequency integrated circuit; CMOS process; CMOS technology; Circuit testing; Electronic equipment testing; Frequency; Integrated circuit interconnections; Joining processes; Performance evaluation; Radiofrequency integrated circuits; Semiconductor device modeling;
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0637-1
Electronic_ISBN :
978-1-4244-0637-1
DOI :
10.1109/EDSSC.2007.4450231
