A reduced hardware general purpose systolic array design

Author

Adibi, A. ; Bonakdar, H.

Author_Institution

Dept. of Electr. Eng., Amirkabir Univ. of Technol., Tehran, Iran

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

310

Abstract

Although there may be many general purpose systolic array design and implementation which could be used to configure some special systolic structure, the degree of their hardware complexity and flexibility is a main question. In this paper we have designed a new systolic array system to realize a range of various algorithms without increasing the hardware structure significantly. The proposed concepts that have been used are: 1) using a novel architecture to allow any number of desired time delays along the data path; 2) dividing instructions and data into two formats-tagged and untagged formats; and 3) suitable processing element (PE) architecture design

Keywords

delays; systolic arrays; general purpose systolic array design; hardware complexity; processing element architecture design; reduced hardware design; tagged format; time delays; untagged format; Algorithm design and analysis; Communication system control; Control systems; Delay effects; Delay systems; Displays; Hardware; Pipeline processing; Switches; Systolic arrays;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519246

Filename

519246