Title :
A Markov chain modelling technique for evaluating pipelined processor designs
Author :
Unwala, Ishaq H. ; Cragon, Harvey G.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
A pipelined processor is a finite state machine and its performance can be evaluated using state transition probabilities obtained from analyzing dynamic instruction traces. The theoretical foundation for Markov chain modeling technique is described. Implementation of an analyzer based Markov chain technique is discussed and results presented
Keywords :
Markov processes; delays; finite state machines; performance evaluation; pipeline processing; probability; FSM; MIPS analyzer; Markov chain modelling technique; dynamic instruction traces; finite state machine; pipelined processor designs; state transition probabilities; Automata; Computer aided instruction; Mathematical model; Performance analysis; Pipelines; Process design; Steady-state; Upper bound;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519248
