PASSOS: a different approach for assignment and scheduling for power, area and speed optimization in high-level synthesis

Author

Martin, R. San ; Knight, J.P.

Author_Institution

Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

339

Abstract

This paper presents a high-level (behavioral) synthesis method that takes advantage of digit-serial arithmetic to minimize power consumption, transistor counts and delays. Genetic algorithms are used for simultaneous scheduling and assignment to obtain significant savings and improvements compared with parallel (32-bit) implementations and/or the best results reported in the literature

Keywords

application specific integrated circuits; circuit CAD; circuit optimisation; delays; digital arithmetic; genetic algorithms; high level synthesis; integrated circuit design; scheduling; ASIC design; PASSOS; area optimization; assignment; behavioral synthesis method; delays; digit-serial arithmetic; genetic algorithms; high-level synthesis; power consumption; power optimization; scheduling; speed optimization; transistor counts; Adders; Arithmetic; Clocks; Delay; Energy consumption; Flow graphs; Genetic algorithms; Optimization methods; Silicon; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519252

Filename

519252