Title :
Architecture driven layout synthesis techniques for CA-type FPGAs
Author :
Dasari, A.K. ; Ramineni, N. ; Naveen, B. ; Chrzanowska-Jeske, Malgorzata
Author_Institution :
Dept. of Electr. Eng., Portland State Univ., OR, USA
Abstract :
Predominantly local connections in new cellular architecture FPGAs present a challenge to CAD tool developers. In this paper we discuss new methodologies for low-level synthesis of digital circuits, to cellular architecture (CA) Field Programmable Gate-Arrays (FPGA). The design representation on logic level of abstraction is created or restructured in such a way that it resembles the architecture of FPGA as close as possible. The resulting structure is therefore easy to map, and a number of logic cells used for routing L minimized. Layout synthesis methods using different design representations are discussed and compared
Keywords :
cellular arrays; circuit layout CAD; field programmable gate arrays; integrated circuit layout; logic CAD; network routing; CAD; FPGA layout; architecture driven synthesis; cellular architecture; digital circuits; field programmable gate-arrays; layout synthesis techniques; low-level synthesis; Binary trees; Circuit synthesis; Design automation; Digital circuits; Electronics packaging; Field programmable gate arrays; Logic arrays; Logic circuits; Logic design; Routing;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519269
