Design and implementation of a fast and compact residue-based semi-custom VLSI arithmetic chip

Author

Hiasat, Ahmad A. ; Abdel-Aty-Zohdy, Hoda S.

Author_Institution

Dept. of Electr. & Syst. Eng., Oakland Univ., Rochester, MI, USA

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

428

Abstract

Design and implementation of a residue-based adder/subtractor/multiplier arithmetic TinyChip for the moduli set (2 ⁿ-1,2ⁿ,2ⁿ+1) is addressed in this paper. The unit realization adopts CMOS semi-custom VLSI design, using Octtools-5.0 with the standard cell MSU2-3 library. The implemented chip has the advantage of reduced delay time and hardware requirements. Thus, it can support real-time one and two dimensional signal processing applications. The design does not have dynamic range limitations due to the absence of memory, therefore, this implementation can be expanded for better reliability. Performance of the system is estimated to be 18 million residue arithmetic operations per second on 2 μm process

Keywords

CMOS logic circuits; VLSI; application specific integrated circuits; circuit CAD; digital signal processing chips; integrated circuit design; logic CAD; real-time systems; residue number systems; 2 micron; ALU; CMOS semicustom VLSI design; DSP applications; Octtools-5.0; adder; fast compact implementation; multiplier; one dimensional signal processing; real-time signal processing; residue-based arithmetic chip; semicustom VLSI chip; standard cell MSU2-3 library; subtractor; two dimensional signal processing; Algorithm design and analysis; Arithmetic; Dynamic range; Hardware; Libraries; Logic; Microelectronics; Signal processing; Signal processing algorithms; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519272

Filename

519272