A 200-MHz CMOS x/sin(x) digital filter for compensating D/A converter frequency response distortion in high-speed communication systems

A 200-MHz 11-tap FIR (finite-impulse response) digital filter for compensating the sin(x)/x spectrum distortion introduced by D/A (digital-to-analog) converters has been designed and fabricated in a 1-μm CMOS technology. This filter chip was designed mainly to operate with a high-speed all-digital QAM (quadrature amplitude modulation) modulator chip for digital radio applications. A bit-level pipelined transpose-form carry-save architecture using simple powers-of-two coefficients was used to achieve high throughput. The filter design and VLSI implementation issues, which play important roles in determining the maximum throughput as well as the chip complexity, are discussed. The features of the filter chip are summarized as follows: >200-MHz maximum sampling rate (tested): 3.45×4.25-mm ² die area (1.91×3.28-mm² core area); 14000 transistors; 2-W power dissipation at 200 MHz; 14-b maximum input wordlength; 16-b internal wordlength; 8~14-b selectable rounded output wordlength; two´s complement data format; and 15-clock-cycle pipeline latency