A GSM 2+ conversion signal processor for continuous full-duplex EDGE/GPRS applications

This conversion signal processor (CSP) handles all classes of EGPRS (classes 1 to 29) and is fabricated in a 0.30/spl mu/m, 3V CMOS process. It is capable of handling all eight consecutive slots for both transmit and receive simultaneously, in contrast to current products which support only 1 to 4 slots (class 8 and 12), and only half-duplex operation. Low power design features include dedicated signal processing functions, a software-programmable GSM-optimized timing control engine extended to support efficient multi-slot operation, analog blocks which power up quickly only when needed, to minimize standby or start-up power. The 100-pin FSBGA chip also includes a complete voiceband CODEC with 16/spl Omega/ speaker drivers, auxiliary DACs, A5 ciphering, and a 32kHz crystal oscillator.