Title :
Analog chip design with Mentor Graphics for submission to the MOSIS foundry interface
Author :
Eatherton, William ; Pottinger, Hardy J.
Author_Institution :
Dept. of Electr. Eng., Missouri Univ., Rolla, MO, USA
Abstract :
This paper presents the previously undocumented steps in CMOS analog chip design for MOSIS fabrication using the commercial Mentor Graphics tool set. The focus of the design process presented is achieving maximum correlation between simulation and testing. Two example designs are presented for illustration. The primary example is an inverting amplifier and the second is a voltage controlled oscillator
Keywords :
CMOS analogue integrated circuits; circuit CAD; circuit layout CAD; engineering graphics; integrated circuit design; CMOS analog chip design; MOSIS fabrication; MOSIS foundry interface; Mentor Graphics tool set; commercial tool set; Analytical models; Chip scale packaging; Circuit simulation; Costs; Educational programs; FETs; Fabrication; Foundries; Graphics; Process design;
Conference_Titel :
Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
Conference_Location :
Lafayette, LA
Print_ISBN :
0-7803-2428-5
DOI :
10.1109/MWSCAS.1994.519276
