A pipelined neural computer for hierarchical pattern recognition

Author

Hung, A. ; Jullien, G.A. ; Kumar, S. ; Coward, A.

Author_Institution

VLSI Res. Group, Windsor Univ., Ont., Canada

Volume

1

fYear

1994

fDate

3-5 Aug 1994

Firstpage

495

Abstract

This paper describes the architecture and circuit techniques used for a neural network compute engine. The neural network application is for general pattern recognition and the architecture is based on an adaptive connection network with majority gates acting as neurons. The paper discusses the training/recall algorithms associated with the network, followed by a detailed explanation of the Neural Computer Engine used in the hardware implementation. We focus specifically on the circuit details of the engine including integrated current sensing TSPC latches and switching tree transistor arrays

Keywords

neural net architecture; pattern recognition; pipeline processing; adaptive connection network; architecture; circuitry; hardware; hierarchical pattern recognition; integrated current sensing TSPC latches; majority gates; neural network compute engine; pipelined neural computer; recall algorithm; switching tree transistor arrays; training algorithm; Adaptive systems; Application software; Circuits; Computer architecture; Computer networks; Engines; Neural network hardware; Neural networks; Neurons; Pattern recognition;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on

Conference_Location

Lafayette, LA

Print_ISBN

0-7803-2428-5

Type

conf

DOI

10.1109/MWSCAS.1994.519286

Filename

519286