2.4 and 2.5 GHz miniature, low-noise oscillators using surface transverse wave resonators and a SiGe sustaining amplifier

Next generation analog-to-digital converters (ADC) are challenged to achieve 100 MHz bandwidth with 100 dB signal-to-noise ratio (SNR) and 100 dB spurious-free dynamic range (SFDR). For such ADC, clock jitter can easily become the limiting factor on performance. This paper describes the development of 2.4 GHz and 2.5 GHz miniature, low-noise oscillators intended to provide the low-jitter clock source for high-performance ADC. The primary design goals for the oscillator are to achieve an integrated jitter of 10-30 fs and to fit within a volume of 0.33 cm³ (0.02 in³). To meet the low-jitter objective, the oscillator is designed for low, close-in phase noise as well as for a low, wideband phase noise floor. Low, close-in phase noise and small size are achieved through the use of a surface transverse wave (STW) resonator as the stabilization element along with a SiGe sustaining amplifier. SiGe enables the sustaining amplifier to provide the excellent 1/f noise performance of silicon at GHz frequencies. A low, wideband noise floor is achieved through the combination of high oscillator loop power and low noise figure, which are simultaneously attained through a two-stage sustaining amplifier design. Measurements performed on free-running prototype oscillators demonstrate a phase noise of -107 dBc/Hz at a 1 kHz offset from the carrier and a wideband noise floor of -175 dBc/Hz, with a resulting integrated jitter of 19 fs. The oscillators provide 5 dBm of RF output power and consume 0.37 W from a 3.3 V power supply. The prototype oscillator circuitry consumes a printed circuit board area of only 11 by 13 mm². Ongoing work is currently in progress to improve the sustaining amplifier close-in phase noise by 15 dB, further reduce the wideband noise floor, and make the oscillator voltage tunable. A package that minimizes the vibration sensitivity of the STW resonator is also in development.