Low-Power Area-Efficient Decimation Filters in Sigma-Delta ADCs

Author

Yi, Feng ; Wu, Xiaobo ; Xu, Jian

Author_Institution

Zhejiang Univ., Hangzhou

fYear

2007

fDate

20-22 Dec. 2007

Firstpage

833

Lastpage

836

Abstract

The performances of different structures for Sine filters were analyzed and compared in this paper. To reduce their power consumption and chip area, a new optimum method was proposed. And it was implemented in poly-phase structure and direct-realization structure respectively for verification. In addition, the low-power area-efficient optimization scheme for decimation filters in Sigma-Delta ADCs was also discussed. All simulation results were obtained under supply voltage of 1.62 V using TSMC 0.18 mum CMOS technology. The results showed that, compared to CIC, 36% area and 50% power were saved for poly-phase structure and 64% power consumption was reduced for direct-realization structure.

Keywords

CMOS integrated circuits; analogue-digital conversion; low-power electronics; power consumption; CMOS technology; Sigma-Delta ADCs; Sine filters; analog-to-digital converters; direct-realization structure; low-power area-efficient decimation filters; low-power area-efficient optimization; poly-phase structure; power consumption; sigma-delta ADCs; supply voltage; CMOS technology; Delta-sigma modulation; Digital filters; Energy consumption; Finite impulse response filter; Frequency; Hip; Performance analysis; Performance evaluation; Transfer functions;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on

Conference_Location

Tainan

Print_ISBN

978-1-4244-0637-1

Electronic_ISBN

978-1-4244-0637-1

Type

conf

DOI

10.1109/EDSSC.2007.4450255

Filename

4450255