DocumentCode
2983907
Title
Block sampling rate conversion for delay reduction
Author
Zou, Xiaoxia ; Muramatsu, Shogo ; Kiya, Hitoshi
Author_Institution
Tokyo Metropolitan Univ., Japan
Volume
4
fYear
1997
fDate
9-12 Jun 1997
Firstpage
2357
Abstract
A new implementation method for sampling rate conversion (SRC) is discussed in this work. Since the proposed method performs sampling rate conversion in a block way via FFT and inverse FFT (IFFT), we call the sampling rate conversion in this case the block sampling rate conversion (BSRC). The proposed method can reduce the additional input-output delay resulted from the use of FFT and trade-off it against the computational complexity more easily, compared with other FFT-based approaches
Keywords
computational complexity; delays; fast Fourier transforms; inverse problems; signal sampling; FFT; block sampling rate conversion; computational complexity; input-output delay; inverse FFT; Adaptive signal processing; Added delay; Computational complexity; Convolution; Digital signal processing; Filtering; Finite impulse response filter; Real time systems; Sampling methods; Signal sampling;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1997. ISCAS '97., Proceedings of 1997 IEEE International Symposium on
Print_ISBN
0-7803-3583-X
Type
conf
DOI
10.1109/ISCAS.1997.612796
Filename
612796
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