• DocumentCode
    298415
  • Title

    Simulating early failure in integrated circuits

  • Author

    Moosa, Mohamed S. ; Poole, Kelvin F.

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Clemson Univ., SC, USA
  • Volume
    1
  • fYear
    1994
  • fDate
    3-5 Aug 1994
  • Firstpage
    728
  • Abstract
    A layout-level Monte-Carlo simulator capable of predicting the probability of defect-related early failure in the metal-interconnect subsystem of integrated circuits is presented. The interconnect is decomposed into distinct layout-level objects, namely contiguous metal runs and vias, and user-defined cumulative distribution functions are used to determine the probability of failure. The failure distributions for nets, which are sets of interconnected layout-objects, are obtained by combining the distributions of their component objects. System reliability is obtained by sampling from the reliability network comprising all nets. Variance reduction techniques are used wherever possible to improve the statistical confidence in estimates made. A prototype that interfaces directly with commercially used CAD software has been implemented. Results provide a qualitative verification of the methodology and show that failures due to defects are significant during the first few years of system operation
  • Keywords
    Monte Carlo methods; circuit analysis computing; circuit layout CAD; digital simulation; failure analysis; integrated circuit interconnections; integrated circuit layout; integrated circuit reliability; probability; CAD software; contiguous metal runs; defect-related early failure; distinct layout-level objects; early failure simulation; failure probability; layout-level Monte-Carlo simulator; metal-interconnect subsystem; reliability network; statistical confidence; user-defined cumulative distribution functions; variance reduction techniques; Circuit simulation; Computational modeling; Distribution functions; Integrated circuit interconnections; Integrated circuit layout; Kelvin; Predictive models; Probability; Semiconductor device reliability; Semiconductor device testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 1994., Proceedings of the 37th Midwest Symposium on
  • Conference_Location
    Lafayette, LA
  • Print_ISBN
    0-7803-2428-5
  • Type

    conf

  • DOI
    10.1109/MWSCAS.1994.519394
  • Filename
    519394