DocumentCode :
2984205
Title :
Full compensated Depletion-Mode MOS-Capacitor for pure digital technology low voltage switched-capacitor applications
Author :
Shujuan, Yin ; Yihe, Sun ; Xiangyu, Li
Author_Institution :
Tsinghua Univ., Beijing
fYear :
2007
fDate :
20-22 Dec. 2007
Firstpage :
913
Lastpage :
916
Abstract :
A full compensated depletion-mode MOS capacitor is presented in this article. The capacitor is composed of MOS depletion capacitors which are biased appropriately to extend available usable voltage range. The capacitor is suitable for state-of-art technology and low-voltage switched capacitor applications. Completely digital technology cuts the cost down heavily. The voltage-dependence and temperature-dependence of the capacitor are much smaller compared with series and parallel compensated depletion-mode MOS capacitors. Theoretical analysis and HSPICE simulations show that the capacitor achieves a density of 0.52 fF/mum2 and a temperature-dependence coefficient of 0.096 ppm/C. A much smaller voltage-dependence square coefficient of 57.2 ppm/V makes it superior in full differential switched-capacitor applications.
Keywords :
MOS capacitors; MOS digital integrated circuits; switched capacitor networks; HSPICE simulation; depletion-mode MOS-capacitor; digital technology; low voltage switched-capacitor applications; Analytical models; CMOS process; CMOS technology; Channel bank filters; Costs; Low voltage; MOS capacitors; MOSFET circuits; Parasitic capacitance; Sun;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits, 2007. EDSSC 2007. IEEE Conference on
Conference_Location :
Tainan
Print_ISBN :
978-1-4244-0637-1
Electronic_ISBN :
978-1-4244-0637-1
Type :
conf
DOI :
10.1109/EDSSC.2007.4450274
Filename :
4450274
Link To Document :
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