DocumentCode
2984267
Title
A 19 GHz 0.5 mW 0.35 /spl mu/m CMOS frequency divider with shunt-peaking locking-range enhancement
Author
Hui Wu ; Hajimiri, A.
Author_Institution
California Inst. of Technol., Pasadena, CA, USA
fYear
2001
fDate
7-7 Feb. 2001
Firstpage
412
Lastpage
413
Abstract
A frequency divider is an essential building block and one of the major sources of power dissipation in widely-used frequency synthesizers. As the output frequency of the synthesizer increases, the trade-off between the speed and power dissipation of dividers becomes more critical. Narrow-band injection-locked frequency dividers (ILFD) dissipate a fraction of the energy stored in the tank, which is determined by the quality factor, Q, of the resonator, in every cycle. Therefore, they have fundamentally lower power dissipation than wide-band dividers. Due to their narrow-band nature, ILFDs work in a limited frequency range (locking range). In this paper, shunt-peaking is used as an approach to increase the locking range and lower the power dissipation at higher frequencies.
Keywords
CMOS analogue integrated circuits; frequency dividers; 0.35 micron; 0.5 mW; 19 GHz; CMOS narrow-band injection-locked frequency divider; frequency synthesizer; locking range; power dissipation; quality factor; resonator; shunt peaking; Energy loss; Frequency conversion; Frequency synthesizers; Inductors; Narrowband; Power dissipation; Power measurement; Tail; Voltage; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International
Conference_Location
San Francisco, CA, USA
ISSN
0193-6530
Print_ISBN
0-7803-6608-5
Type
conf
DOI
10.1109/ISSCC.2001.912698
Filename
912698
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