Title :
Reconfigurable Platform Evaluation Through Application Mapping And Performance Analysis
Author :
Majzoub, Sohaib ; Saleh, Resve ; Diab, Hassan
Author_Institution :
SoC Res. Lab, British Columbia Univ., Vancouver, BC
Abstract :
The area of reconfigurable computing has received considerable interest in both its forms: the FPGA and coarse grain hardware. Since the field is still in its infancy, it is important to perform hardware analysis and evaluation of certain key applications on target reconfigurable architectures to identify potential limitations and improvements. This paper presents analysis of the advanced encryption standard (Rijndael), which is then implemented on a coarse grain reconfigurable platform (MorphoSys). We provide details of mapping Rijndael and present an analysis to highlight the apparent bottlenecks. We suggest methods of upgrading and enhancing the MorphoSys hardware accordingly
Keywords :
cryptography; field programmable gate arrays; performance evaluation; reconfigurable architectures; FPGA; MorphoSys coarse grain reconfigurable platform; Rijndael advanced encryption standard; application mapping; coarse grain hardware; performance analysis; reconfigurable architectures; reconfigurable computing; reconfigurable platform evaluation; Algorithm design and analysis; Context; Cryptography; Design engineering; Field programmable gate arrays; Hardware; Parallel processing; Performance analysis; Reconfigurable architectures; Signal design; AES; Cryptography; Hardware Evaluation; MorphoSys; Performance Analysis; Reconfigurable Systems; Rijndael;
Conference_Titel :
Signal Processing and Information Technology, 2006 IEEE International Symposium on
Conference_Location :
Vancouver, BC
Print_ISBN :
0-7803-9753-3
Electronic_ISBN :
0-7803-9754-1
DOI :
10.1109/ISSPIT.2006.270852
