SiGe BiCMOS broadband phase-aligner circuit from 1 Gb/s to 11 Gb/s

Author

Hofmann, R. ; Jelonnek, B. ; Kling, H. ; Splett, A. ; Koenig, E.

Author_Institution

Siemens AG, Ulm, Germany

fYear

2001

fDate

7-7 Feb. 2001

Firstpage

420

Lastpage

421

Abstract

The circuit is implemented as the interface between two BiCMOS chips for the TX frontend in second- and third-generation basestations. No clock recovery is necessary in these applications. The first chip translates the incoming IQ-data stream from the baseband into a serial output data stream with a bit rate up to 8.5Gb/s for CDMA-, GSM- and EDGE applications in the 2GHz range. This data stream already contains the antenna signal. To achieve this functionality, the first chip includes digital filters, interpolating stages and a /spl Sigma//spl Delta/ modulator. The second chip with input stage consisting of the presented phase-aligner circuit is a digital to analog converter (DAC).

Keywords

BiCMOS integrated circuits; Ge-Si alloys; cellular radio; code division multiple access; interpolation; mixed analogue-digital integrated circuits; semiconductor materials; sigma-delta modulation; /spl Sigma//spl Delta/ modulator; 1 to 11 Gbit/s; 2 GHz; BiCMOS broadband phase-aligner circuit; CDMA; EDGE; GSM; SiGe; TX frontend; antenna signal; digital filters; digital to analog converter; incoming IQ-data stream; interpolating stages; second-generation basestations; serial output data stream; third-generation basestations; BiCMOS integrated circuits; CMOS technology; Clocks; Counting circuits; Delay; Germanium silicon alloys; Integrated circuit technology; Logic arrays; Silicon germanium; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2001. Digest of Technical Papers. ISSCC. 2001 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-6608-5

Type

conf

DOI

10.1109/ISSCC.2001.912702

Filename

912702