A Novel Sub-Micron Semiconductor Gap Fill Integrated Processes

To investigate the semiconductor process module integration and technology on optimal integrated lithography processes on sub-micron semiconductor process integration. As duel damascene integration copper process is complicated and margin in semiconductor process. It has been common knowledge that pattern collapse of this type process could be prevented by optimal the process module. Proposed novel semiconductor process on various pattern design and deep pattern aspect ratio effects of sub-micron CMOS semiconductor BEOL (Back-End-Of-Line) structure was included in this study.