A new architecture for a cyclic algorithmic DA converter

In this paper, a new architecture for cyclic algorithmic DA converters will be proposed. The upper bound for the maximum number of converted bits will be expressed in the mismatch error of the factor 1/2. It turns out that the number of relevant bits is twice the number achieved in the conventional technique under the same assumed mismatch error, without raising the conversion time above n-times a single bit conversion. An implementation in switched-current technique is treated