An Improved AHB Bus Frame Adapted to a High-Performance Network Security Accelerator

With the maturity of SOC, IC designers not only consider IP (Intellectual Property) level issues such as performance, the area and power dissipation, but also system-level issues such as bus on-chip, which has an effect on system performance, power dissipation, chip area and system upgrade. This paper proposes an improved AHB bus frame adapted to a high-performance Network Security Accelerator (NSA), which processes giga bits per second for the bulk cipher, as well as 3000 times per second for the RSA key-exchanges of 1024 bits, 1200 times scalar multiplications of 256 bits for general curve over GF(p), and 1500 times for those over GF(2"). In this paper, dual one-way 64-bit buses are proposed. The improved bus frame settles issues of data congestion, the bus handover and the iterant transfer for the same data. 25.6 Gbps data transfer rate is attainable with 200 MHz clock frequency. The basic transfer mode of the improved bus is burst transfer which reaches up to 64 beats. This bus frame meets the need of high speed transfer for high-performance NSA. Meanwhile, eliciting address bus in the improved bus frame makes the issues of power consumption, the chip area and the complexity of routing for large system alleviative.